The present invention relates to a method of forming indium-doped channel regions in a semiconductor substrate, whereby a desired retrograde-shaped indium concentration distribution profile is obtained. The present invention has particular utility in the manufacture of MOS-type transistor devices and semiconductor integrated circuits with improved processing methodology resulting in increased device reliability and performance characteristics. The present invention is also useful in the manufacture of CMOS devices and has particular applicability in fabricating high-density integration semiconductor devices with design features below about 0.18 xcexcm, e.g., about 0.15 xcexcm.
The escalating requirements for high density and performance associated with ultra-large scale integration (ULSI) semiconductor devices, such as are currently manufactured or contemplated, require design features of 0.18 xcexcm and below, such as 0.15 xcexcm and below, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for economic competitiveness. The reduction of design features to 0.18 xcexcm and below challenges the limitations of conventional semiconductor manufacturing techniques.
As feature sizes of MOS and CMOS devices have decreased to the sub-micron range, so-called xe2x80x9cshort-channelxe2x80x9d effects have arisen which tend to limit device performance. For n-channel MOS transistors, the major limitation encountered is caused by hot-electron-induced instabilities. This problem occurs due to high electrical fields between the source and the drain, particularly near the drain, such that charge carriers, either electrons or holes, are injected into the gate or semiconductor substrate. Injection of hot carriers into the gate can cause gate oxide charging and threshold voltage instabilities which accumulate over time and greatly degrade device performance. In order to counter and thus reduce such instabilities, shallow junction, lightly- or moderately-doped source/drain extension type transistor structures have been developed.
For p-channel transistors, the major xe2x80x9cshort-channelxe2x80x9d effect which limits device performance arises from xe2x80x9cpunch-throughxe2x80x9d effects which occur with relatively deep junctions. In such instances, there is a wider sub-surface depletion effect and it is easier for the field lines to go from the drain to the source, resulting in the above-mentioned xe2x80x9cpunch-throughxe2x80x9d current problems and device shorting. To minimize this effect, relatively shallow junctions are employed in forming p-channel MOS-type transistors.
The most satisfactory solution to date of hot carrier instability problems of MOS and CMOS-type sub-micron-dimensioned devices is the provision of lightly- or moderately-doped source/drain extensions driven just under the gate region, while the heavily-doped source/drain regions are laterally displaced away from the gate by the use of a pair of spacers on opposite sidewalls of the gate. Such structures are particularly advantageous because they do not have problems with large lateral diffusion and the channel length can be set precisely.
In operation of such devices, an input voltage is applied to the gate electrode and an output voltage is developed across the source and drain terminals. When the input voltage is applied to the gate electrode, a transverse electrical field is set up in the channel region between the source and drain regions. Variation of the transverse electrical field makes it possible to vary the conductance of the channel region, whereby an electric field controls the flow of current through the channel region between the source and drain regions. The channel region typically is lightly doped with an impurity of conductivity type opposite that of the source/drain regions, and the dopant impurity concentration distribution profile is typically uniform in the direction extending downwardly from the substrate surface. Such type MOS structures, however, are susceptible to xe2x80x9clatch upxe2x80x9d, wherein a very low resistance path is established between the VSS and VDD power lines, resulting in excessive current flow across the power supply terminals. Susceptibility to xe2x80x9clatch-upxe2x80x9d arises from the presence of complementary parasitic bipolar transistor structures, and is particular problematic with CMOS devices because such bipolar structires can electrically interact, in the manner of a pnpn diode. In the absence of triggering currents, such diodes act as reverse-biased junctions and do not conduct. However, it is possible for triggering currents to be established in a variety of ways during abnormal circuit operating conditions. Since many such parasitic pnpn structures can be present within a single chip, it is possible to trigger any one of them into a xe2x80x9clatch upxe2x80x9d condition and thus cause cessation of proper device functioning or even destroy the device due to locally high power dissipation.
One approach for control or elimination of xe2x80x9clatch upxe2x80x9d is the provision of retrograde doping profiles, i.e., a dopant impurity concentration distribution profile exhibiting a concentration peak deep below the substrate surface. Retrograde Channel Profiles (xe2x80x9cRCPxe2x80x9d) are employed in MOS and CMOS technology to reduce threshold voltage (VT) roll-off, i.e., sudden decrease of VT at very small (xe2x80x9csub-nominalxe2x80x9d) device lengths. However, for RCP to be effective, the profile itself should meet certain criteria. First, the peak concentration should be located at an optimal depth from the surface because, on the one hand, if the impurity concentration peak is formed too close to the substrate surface, VT must be increased, while on the other hand, if the impurity concentration peak is too far below the substrate surface, the tendency for xe2x80x9clatch upxe2x80x9d will not be reduced or eliminated. Second, the profile along a vertical cut should be rather sharp, e.g., a delta function.
The use of boron doping (i.e., p-type doping) techniques for forming such RCP structures in the case of n-channel MOS and CMOS devices is problematic, principally due to the ease with which boron atoms diffuse in silicon semiconductor substrates. The rapidity of boron dopant atom diffusion upon thermal treatment for post-implantation activation/lattice damage relaxation disadvantageously results in a relatively flat or broadly-peaked concentration distribution profile rather than the desired sharply peaked profile.
The use of indium as an alternative p-type dopant to boron for RCP formation incurs a drawback in that indium easily diffuses into silicon oxide (e.g., SiO2) gate insulator layers, resulting in degradation of the gate oxide reliability. RCP formation with satisfactorily sharply-peaked profiles utilizing indium as a p-type dopant for channel regions of silicon-based MOS and CMOS transistor devices can be effected by implanting indium-containing ions In+ into a portion of the surface 2 of a silicon substrate 1 where a channel region is to be later formed at dosages and energies typically in the ranges of 1xc3x971012xe2x88x928xc3x971013 ions/cm2 and 80-140 KeV, respectively, as illustrated by curve 3 of FIG. 1(A). As is evident from the figure, indium implantation under such conditions results in a retrograde-shaped doping concentration profile extending to a depth d1 below substrate surface 2, with a maximum (or peak) indium concentration cmax at a depth dmax. However, as is apparent from FIG. 1(B), which illustrates the state after thin gate insulator layer 6 formation on surface 2, indium atoms and/or ions 4 remaining on the substrate surface and/or implanted in the uppermost stratum 5 of the substrate, rapidly diffuse into and degrade the reliability and insulative properties of the thin gate insulator layer 6 when the latter is of a silicon oxide thermally grown or otherwise formed on the substrate surface 2, or when the latter is subjected to subsequent device formation processing at elevated temperatures conducive to dopant diffusion. Residual, post-implantation indium present on the substrate surface 2 is extremely difficult to remove by conventional chemical-based methodologies, e.g., etching, without incurring undesirable surface damage. Moreover, existing etching methods are unable to substantially completely remove implanted indium ions and/or atoms from a sufficiently deep upper stratum of substrate 1 as to effectively preclude diffusion of indium into the subsequently formed thin gate oxide layer 6.
Thus, a need exists for improved semiconductor manufacturing methodology for fabricating MOS and CMOS transistors and related devices which does not suffer from the above-described drawbacks associated with the rapid diffusion of indium in silicon oxide-based thin gate insulator layers and the difficulty of removal of residual indium ions and/or atoms from implanted substrate surfaces by conventional chemical techniques. Moreover there exists a need for an improved process for fabricating MOS transistor-based devices with reduced short-channel effects such as xe2x80x9clatch upxe2x80x9d, which process is fully compatible with conventional process flow and provides increased manufacturing throughput and product yield.
An advantage of the present invention is an improved method for forming an indium-doped retrograde-shaped doping profile in a semiconductor substrate, having a preselected maximum or peak indium concentration at a preselected depth below the surface of the substrate and a substantially indium-free stratum extending for a preselected depth below the substrate surface.
Another advantage of the present invention is an improved method for forming a MOS or CMOS semiconductor device comprising a semiconductor substrate having an indium-doped retrograde-shaped channel doping profile and an overlying thin gate insulator layer substantially free of diffused indium.
Yet another advantage of the present invention is a silicon-based, MOS-type transistor device having a channel region comprising an indium-doped retrograde-shaped doping profile and a silicon oxide thin gate insulator layer substantially free of diffused indium ions and/or atoms.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the instant invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to an aspect of the present invention, the foregoing and other advantages are achieved in part by a method of forming an indium-doped semiconductor having a retrograde-shaped indium doping concentration profile, which method comprises the sequential steps of:
(a) providing a semiconductor substrate having a surface;
(b) introducing indium-containing dopant atoms and/or ions into a portion of the surface to form a retrograde-shaped indium doping concentration profile extending from the surface to a first depth below the surface; and
(c) removing substantially all of the introduced indium dopant from the surface and from a stratum of the substrate extending from the surface down to a second depth less than the first depth.
In embodiments according to the present invention, step (a) comprises providing a silicon substrate; step (b) comprises forming a retrograde-shaped indium doping concentration profile having a preselected first depth and a maximum indium concentration at a preselected depth by implanting indium-containing ions at a dosage of from about 1xc3x971012 to about 8xc3x971013 ions/cm2 at an energy of from about 80 to about 140 KeV; step (c) comprises removing substantially all of the indium dopant ions and/or atoms from the surface and from a stratum extending from the surface to a preselected depth by rapid thermal annealing (RTA) at a temperature of about 1,000-1,050xc2x0 C. for about 10-20 seconds; and further comprising the steps of: (d) providing a layer stack comprising a substantially indium-free, thin silicon oxide gate insulator layer and an electrically conductive gate electrode layer successively formed over the portion of the surface; and (e) forming a pair of source/drain regions in the substrate adjacent opposite lateral sides of the layer stack.
According to another aspect of the present invention, a method of manufacturing a MOS transistor device having a channel region comprising a retrograde-shaped indium doping concentration profile is provided, which method comprises the sequential steps of:
(a) providing a silicon semiconductor substrate having a surface;
(b) implanting indium-containing dopant ions into a portion of the surface to form a retrograde-shaped indium doping concentration profile extending from the surface to a first depth;
(c) rapid thermal annealing the substrate to remove substantially all of the implanted indium ions and/or atoms from the surface and from a stratum of the substrate extending from the surface to a second depth less than the first depth;
(d) successively forming a substantially indium-free, thin silicon oxide gate insulator layer and a heavily-doped polysilicon gate electrode layer over the portion of the surface;
(e) forming a pair of source/drain regions in the substrate at laterally opposed ends of the surface portion; and
(f) forming ohmic contacts to the gate electrode layer and the pair of source/drain regions.
According to embodiments of the present invention, step (b) comprises forming a retrograde-shaped indium doping concentration profile extending to a preselected first depth and a maximum indium concentration at a preselected depth by implanting indium-containing ions at a dosage of from about 1xc3x971012 to about 8xc3x971013 ions/cm2 at an energy of from about 80 to about 140 KeV; step (c) comprises removing substantially all of the implanted dopant ions from the surface and from a stratum extending from the surface to the preselected second depth by rapid thermal annealing the substrate at a temperature of about 1,000-1,050xc2x0 C. for about 10-20 seconds; step (d) comprises forming a silicon oxide thin gate insulator layer about 25-50 xc3x85 thick; and step (f) comprises forming refractory metal silicide ohmic contacts to the gate electrode layer and the pair of source/drain regions.
According to yet another aspect according to the present invention, a semiconductor body is provided, comprising:
a silicon semiconductor substrate having an indium-free surface;
a first, substantially indium-free stratum formed beneath a portion of the substrate surface and extending to a first depth; and
a second, indium-doped stratum beneath the first stratum, the second stratum comprising a retrograde-shaped indium doping concentration profile extending from the first depth to a second depth and having a maximum indium concentration at a third depth intermediate the first and second depths.
According to still another aspect of the present invention, an MOS transistor device comprising the above semiconductor body having a retrograde-shaped indium doping concentration profile is provided, comprising:
a layer stack formed on the portion on the portion of the surface of the semiconductor substrate, the layer stack comprising:
i. a substantially indium-free, thin gate insulator layer in contact with the portion of the surface; and
ii. an electrically conductive gate electrode layer on the gate insulator layer,
a channel region in the substrate below and contiguous with the layer stack, the channel region comprising:
i. the first, substantially indium-free stratum; and
ii. the second, indium-doped stratum having the retrograde-shaped indium doping concentration profile beneath the first stratum;
a pair of source/drain junction regions formed in the substrate at laterally opposed ends of the channel region; and
ohmic contacts to each of the gate electrode layer and source/drain regions.
According to embodiments of the present invention, the semiconductor substrate comprises a monocrystalline silicon wafer; the thin gate insulator layer comprises a silicon oxide layer about 25-50 xc3x85 thick; the gate electrode layer comprises heavily-doped polysilicon; and each of the ohmic contacts comprises an electrically conductive refractory metal silicide.
Additional advantages and aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the method of the present invention. As will become evident, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as limitative.